发明名称 System and method for multi processor memory testing
摘要 A method for testing the memory in a system with two or more processing units is provided that generally involves the following acts. The memory is divided into two or more sections-one for each of the two or more processing units. Thus, each processing unit has an associated memory section. The memory is then checked with each memory section being checked with its associated processing unit. The act of checking the memory includes causing the address of a first encountered faulty location to be stored and causing a flag to be set in response to encountering a second faulty location. Finally, it is determined whether the flag has been set after the memory is checked. If so, a walk-through routine is then performed.
申请公布号 US7143321(B1) 申请公布日期 2006.11.28
申请号 US20000561813 申请日期 2000.04.29
申请人 HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. 发明人 EVERETT GERALD L;DICKEY KENT A
分类号 G06F12/16;G11C29/00;G11C29/08 主分类号 G06F12/16
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