Multiplying phase detector for use in a random data locked loop architecture

摘要

A multiplying phase detector includes a 1^st multiplier, a 2^nd multiplier and a phase error generation module. The 1^st multiplier is operably coupled to multiple an incoming data stream, which is a random data pattern, with a 1^st clock, which is in-phase with the incoming stream of data and is one-half the rate of the incoming stream of data, to produce a 1^st product. In this instance, the 1^st product represents missing transitions in the incoming stream of data. The 2^nd multiplier is operably coupled to multiply the 1^st product with the incoming data stream to produce a modified stream of data. The phase error generation module is operably coupled to generate a phase error based on the modified stream of data and a 2^nd clock, where the phase error represents a phase offset between the modified stream of data and the 2^nd clock.