发明名称 |
Circuit for controlling an enabling time of an internal control signal according to an operating frequency of a memory device and the method thereof |
摘要 |
Provided is a circuit for controlling a data bus connecting a bitline sense amplifier to a data sense amplifier in accordance with a variation of an operating frequency of a memory device, being comprised of a pulse width adjusting circuit for varying a pulse width of an input signal in accordance with the operating frequency of the memory device after receiving the input signal, a signal transmission circuit for buffing a signal outputted from the pulse width adjusting circuit, and an output circuit for outputting a first signal to control the data bus in response to a signal outputted from the signal transmission circuit.
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申请公布号 |
US7142469(B2) |
申请公布日期 |
2006.11.28 |
申请号 |
US20040888220 |
申请日期 |
2004.07.09 |
申请人 |
HYNIX SEMICONDUCTOR INC. |
发明人 |
KIM JI HYUN;NAM YOUNG JUN |
分类号 |
G11C7/00;G11C7/06;G11C7/08;G11C7/10;G11C29/02 |
主分类号 |
G11C7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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