| 摘要 |
A dual-thickness active device layer SOI chip structure is provided. The SOI chip structure has an active device layer, at least one oxide region located at a predetermined position of the active device layer and with a first predetermined depth, at least one trench surrounding the oxide region and having a second predetermined depth greater than the first predetermined depth, and a ground layer connected to the active device layer and the oxide region. The SOI structure further has a first silicon-based wafer and a second wafer. Both wafers are bonded together by wafer bonding. At least two different active device layer thicknesses exist to meet requirements of a wide variety of SOI devices placed thereon, with the setting of the oxide region filled with thermal oxide or other oxide variations.
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