发明名称 |
Semiconductor device having a multilayer interconnection structure, fabrication method thereof, and designing method thereof |
摘要 |
A semiconductor device includes an interconnection structure in which via-plug density is higher in an upper layer part than a lower layer part, wherein the peeling of the lower via-plugs at the time of formation of the upper-via-plugs is avoided by restricting the density of the upper s, defined for a unit area having a size of 50-100 mum for each edge, to be 60% or less.
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申请公布号 |
US7141881(B2) |
申请公布日期 |
2006.11.28 |
申请号 |
US20040939594 |
申请日期 |
2004.09.14 |
申请人 |
FUJITSU LIMITED |
发明人 |
TAKAYAMA TOSHIO;ITOU TETSUYA |
分类号 |
H01L21/768;H01L23/40;H01L21/3205;H01L21/4763;H01L21/70;H01L21/82;H01L23/48;H01L23/52;H01L23/522;H01L23/532 |
主分类号 |
H01L21/768 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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