发明名称 Method and device for generating clock signal
摘要 A method and device for generating a clock signal accurately synchronized with a wobble signal including jitter even if there are manufacturing differences between voltage controlled oscillators. The clock signal generation device includes a voltage controlled oscillator for generating a clock signal corresponding to each of a plurality of oscillation characteristics. The clock signal generation device applies a test voltage to a voltage controlled oscillator with a voltage control device and sequentially identifies a plurality of oscillation characteristics set for the voltage controlled oscillator. The clock signal generation device selects one of the identified oscillation characteristics that has a frequency range with a generally middle part in which the frequency of a wobble signal is located and has a smaller gain.
申请公布号 US7141961(B2) 申请公布日期 2006.11.28
申请号 US20050044736 申请日期 2005.01.27
申请人 SANYO ELECTRIC CO., LTD. 发明人 HIRAYAMA HIDEKI;WATANABE TOMOFUMI;KIYOSE MASASHI
分类号 G01R19/00;H03L7/093;G11B20/00;H03L7/06;H03L7/087;H03L7/099;H03L7/18;H04L27/152 主分类号 G01R19/00
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