| 摘要 |
PROBLEM TO BE SOLVED: To provide a clock tree generating method which can reduce a time necessary for reducing a power consumption and for improving a setup/hold error. SOLUTION: In the clock tree generating method, cells are arranged, a clock tree is temporarily wired, and clock load cells are again arranged so that a wiring length from a clock root pin to the clock terminal of each clock load cell is in a predetermine range (S1 to S5), and delay elements are temporarily wired to the clock tree so that a clock skew and so on satisfy a prescribed value (S6). For a data bus having a setup/hold error, the clock load cells are again arranged so as to have a small slack value, and so on. For a data bus having no setup/hold error, the clock load cells are again arranged so as to be positioned closer to each other (S7 to S12). Finally, the clock skew and so on are readjusted and the location position of the temporarily-arranged delay element on the clock tree is adjusted as the final arrangement (S13, S14). COPYRIGHT: (C)2007,JPO&INPIT
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