| 摘要 |
<P>PROBLEM TO BE SOLVED: To materialize a receiving device capable of restraining a lacking state of content information when a different bit interleave time is switched over. <P>SOLUTION: The receiving device has a delay circuit configured so that shift registers of a plurality of stages are tandem-connected to input data from each stage of the shift register, and a seamless memory 21 comprising a plurality of the delay circuits in which the number of stages of the shift register is different. When a bit interleave time is switched over, data of a broadcasting channel received newly is input from a new shift register stage of the delay circuit, whereby the seamless memory 21 generates a desirable delay signal in compliance with the bit interleave time in the broadcasting channel received newly. <P>COPYRIGHT: (C)2007,JPO&INPIT |
