| 摘要 |
A memory module device and a memory system having the same are provided to obtain desired signal integrity in a memory system having an operation clock frequency over several GHz, by reducing existing capacitive load effect due to command/address signals. A memory module(800a) device comprises First to Nth memory devices(810,820,830). A command/address port is connected to at least one memory device among the memory devices, and transmits write data and a command/address signal. First to Nth data ports are connected to the memory devices respectively, and output read data. A Kth memory device connected to the command/address port re-transmits the write data and the command/address signal to at least another memory device. The Kth memory device includes a repeater re-transmitting the command/address signal to at least another memory device.
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