发明名称 Overlay vernier and method for manufacturing semiconductor device using the same
摘要 An overlay vernier comprises overlay vernier patterns having a layout identical to that of patterns disposed within a real cell. A lower overlay vernier pattern is formed within a scribe line region along with a lower layer pattern as a lower layer of the real cell, and an upper overlay vernier pattern is formed within the scribe line region along with an upper layer pattern as an upper layer of the real cell. The lower overlay vernier pattern and the upper overlay vernier pattern have the same layout as that of the lower layer pattern and the upper layer pattern, respectively. The upper layer pattern and the lower layer pattern disposed within the real cell can be accurately aligned using the degree of overlap between the upper overlay vernier pattern and the lower overlay vernier pattern.
申请公布号 US2006263706(A1) 申请公布日期 2006.11.23
申请号 US20050321131 申请日期 2005.12.28
申请人 HYNIX SEMICONDUCTOR INC. 发明人 YIM DONG G.
分类号 G03F9/00;G03C1/00;G03C5/00 主分类号 G03F9/00
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