| 摘要 |
A memory cell has a selection transistor constituted of an MOS transistor having a gate electrode and a cell transistor constituted of an MOS transistor having the same polarity as the selection transistor, in such a configuration that these two transistors are connected in series. A bit line is connected to a drain region of the selection transistor and a word line is connected to the gate electrode thereof. A gate electrode of the cell transistor is not electrically connected anywhere so as to be in a floating potential state, while a drain region thereof is connected to a source region of the selection transistor. A source line is connected to a source region of the cell transistor.
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