| 摘要 |
A digital data slicing circuit and a method for slicing digital data are provided. The digital data slicing circuit comprises a slicer, a phase locked loop (PLL), a data jitter circuit, and a level calculator. Wherein, the slicer receives a RF signal and a slicing level and outputs a digital signal. The PLL provides a PLL clock based on the received digital signal. The data jitter circuit obtains a jitter signal by comparing the digital signal with the PLL clock, and outputs a jitter error signal by performing a jitter calculation with the jitter signal, the digital signal, and the PLL clock. The level calculator receives the jitter error signal and adjusts and outputs the slicing level.
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