发明名称 |
Stalling CPU Pipeline to Prevent Corruption in Trace While Maintaining Coherency With Asynchronous Events |
摘要 |
A method of preventing trace data first-in-first-out buffer overflow in a pipelined data processor stops new instructions when a trace data first-in-first-out buffer is in danger of overflowing. The method also stalls a predetermined number of pipeline stages in the pipeline ahead of the first pipeline stage. The trace data first-in-first-out buffer is emptied while the pipeline is stalled. On restart, the stalled pipeline stages are restarted ahead of re-enabling new instructions. Asynchronous trigger events received during the stall may be buffered and unrolled in order or merely stored and applied simultaneously on restart.
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申请公布号 |
US2006265574(A1) |
申请公布日期 |
2006.11.23 |
申请号 |
US20060456972 |
申请日期 |
2006.07.12 |
申请人 |
AGARWALA MANISHA;JOHNSEN JOHN M |
发明人 |
AGARWALA MANISHA;JOHNSEN JOHN M. |
分类号 |
G06F9/44;G06F9/455 |
主分类号 |
G06F9/44 |
代理机构 |
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