| 摘要 |
A process is provided for forming a trench capacitor, such as used in a DRAM memory cell, in which the required number of polysilicon deposition steps and planarization steps are reduced. A first region of a first material is formed in the bottom portion of the trench, and a dielectric material for the collar structure is subsequently formed above this region on a portion of the trench sidewalls. A removable material, such as a resist or spin-on glass, is then provided in the trench, overlying the first material and in contact with the lower portion of the collar dielectric material. The upper portion of the collar structure is then removed, after which the removable material is removed to again expose the upper surface of the first region. A second region of a second material, overlying and in contact with the first region, is then formed; the second region has an upper surface below the surface of the substrate. The first and second materials are conducting materials, typically polysilicon. The capacitor thus may be formed with only two polysilicon deposition processes; the interface between the first and second materials is the only interface between conducting materials in the trench.
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