发明名称 |
Aggregated run-to-run process control for wafer yield optimization |
摘要 |
A method for processing wafers in a batch processing tool that optimizes yield by minimizing within batch wafer variation in a wafer process. In a tool having a plurality of available wafer positions for a batch process, the method is useful when less than a full batch of wafers is to be processed. All of the possible wafer position combinations are determined and the within batch variation for each position combination is determined. The wafer position combination resulting in the least amount of within batch variation in the wafer process is then selected as the wafer placement combination for use in the process.
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申请公布号 |
US2006265162(A1) |
申请公布日期 |
2006.11.23 |
申请号 |
US20050123609 |
申请日期 |
2005.05.04 |
申请人 |
HITACHI GLOBAL STORAGE TECHNOLOGIES |
发明人 |
MURO AMELIA C.;WALKER ANDREW C.;WONG YEAK-CHONG |
分类号 |
G01N37/00;G06F19/00 |
主分类号 |
G01N37/00 |
代理机构 |
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地址 |
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