发明名称 |
Data packet arithmetic logic devices and methods |
摘要 |
New instruction definitions for a packet add (PADD) operation and for a single instruction multiple add (SMAD) operation are disclosed. In addition, a new dedicated PADD logic device that performs the PADD operation in about one to two processor clock cycles is disclosed. Also, a new dedicated SMAD logic device that performs a single instruction multiple data add (SMAD) operation in about one to two clock cycles is disclosed.
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申请公布号 |
US7139900(B2) |
申请公布日期 |
2006.11.21 |
申请号 |
US20030602349 |
申请日期 |
2003.06.23 |
申请人 |
INTEL CORPORATION |
发明人 |
GEE COREY;VINNAKOTA BAPIRAJU;MOHAMMADALI SALEEM;ALBEROLA CARL A. |
分类号 |
G06F7/485;G06F9/00;G06F9/302;G06F9/308;G06F9/38 |
主分类号 |
G06F7/485 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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