发明名称 Phase-locked loops
摘要 A phase-locked loop (PLL) is disclosed. One embodiment, among others, includes a PLL that provides a control current and varies the control current in proportion to an inverse of N squared. N is the ratio of the output frequency of the PLL system to the reference frequency of the PLL system. The varying of the control current compensates for bandwidth changes of the PLL system.
申请公布号 US7138839(B2) 申请公布日期 2006.11.21
申请号 US20040849266 申请日期 2004.05.19
申请人 发明人
分类号 H03L7/06;H03L7/00;H03L7/089;H03L7/093;H03L7/107;H03L7/187 主分类号 H03L7/06
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