发明名称 Memory component with improved noise insensitivity
摘要 A memory component comprises a memory cell array, signal inputs, input amplifiers connected to respective ones of the signal inputs, for receiving, amplifying and outputting data, address or control signals, a data, address or control signal generator for the memory cell array, a first supply network for supplying power to the input amplifiers and a second supply network for supplying power to the data, address or control signal generator, wherein the first supply network and the second supply network do not have a direct connection.
申请公布号 US7139206(B2) 申请公布日期 2006.11.21
申请号 US20050031740 申请日期 2005.01.07
申请人 INFINEON TECHNOLOGIES AG 发明人 SCHAEFER ANDRE
分类号 G11C7/02;G11C5/14;G11C7/00;G11C7/10;G11C11/4063;H03F1/26;H03F3/45 主分类号 G11C7/02
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