发明名称 Multiply execution unit for performing integer and XOR multiplication
摘要 A multiply execution unit that is operable to generate the integer product and the XOR product of a multiplicand and a multiplier. The multiply execution unit includes a summing circuit for summing a plurality of partial products. The partial products may be Booth encoded. The summing circuit can generate an integer sum of the plurality of partial products and can generate an XOR sum of the plurality of partial products. The summing circuit includes a first plurality of full adders. The first plurality of full adders each has three inputs, a carry output, and a sum output. The sum outputs of the first plurality of full adders are independent of the value of any carry output in the summing circuit. The summing circuit also includes a second plurality of full adders. The second plurality of full adders each has three inputs, a carry output, and a sum output. The XOR sum is dependent upon at least one of the sum outputs of the first plurality of full adders but is independent of the sum outputs of the second plurality of full adders. The integer sum is dependent upon the sum outputs of at least one of the first plurality of full adders and is also dependent on at least one of the sum outputs of the second plurality of full adders.
申请公布号 US7139787(B2) 申请公布日期 2006.11.21
申请号 US20030354354 申请日期 2003.01.30
申请人 SUN MICROSYSTEMS, INC. 发明人 RARICK LEONARD D.;SHANTZ SHEUELING CHANG;SUNDARAM SHREYAS
分类号 G06F7/52;G06F7/533;G06F7/72;G06F9/44;G06F15/00 主分类号 G06F7/52
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