发明名称 |
Processing unit and processing method |
摘要 |
A digital signal processor configured to perform a Viterbi algorithm includes an instruction fetching unit that fetches instructions and a decoding unit that decodes the instructions fetched by the instruction fetching unit. The digital signal processor also includes an execution unit that executes the instructions decoded by the decoding unit. The execution unit includes an arithmetic logic unit configured to perform a register-register arithmetic logic operation. The arithmetic logic unit compares a first data with a second data, in parallel with a comparison of a third data with a fourth data, and the execution unit outputs new path metrics. Each of the first data, the second data, the third data, and the fourth data is one of four results obtained by adding one of two path metrics to one of two branch metrics.
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申请公布号 |
US7139968(B2) |
申请公布日期 |
2006.11.21 |
申请号 |
US20030748242 |
申请日期 |
2003.12.31 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
YAMANAKA RYUTARO;SUZUKI HIDETOSHI;KABUO HIDEYUKI;OKAMOTO MINORU;STONE KEVIN MARK |
分类号 |
G06F11/10;H03M13/03;H03M13/23;H03M13/41;H04L1/00 |
主分类号 |
G06F11/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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