| 摘要 |
PROBLEM TO BE SOLVED: To further improve process performance relating to a short packet. SOLUTION: The device comprises an SDRAM 16 for storing transmitted and received data for packet transmission, a descriptor 15 for memorizing storage location information of the transmitted and received data, Ethernet (R) controllers 11a, 11b for accessing the transmitted and received data, and a CPU core 10 for controlling the descriptor and the Ethernet (R) controllers at the time of transmitting and receiving the packet. The descriptor and the Ethernet (R) controllers are directly connected via a bus 22, while the descriptor, the SDRAM, the CPU core, and the Ethernet (R) controllers are connected via a bus 21. The Ethernet (R) controllers 11a, 11b access the transmitted and received data via the bus 21 based on the storage location information read via the bus 22. COPYRIGHT: (C)2007,JPO&INPIT
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