发明名称 Method and system for improving integrated circuit manufacturing yield
摘要 A lithographic scanner collects surface height information concurrently with conducting a lithographic scan process. A defect identification module identifies wafers having a surface height metric greater than a determined threshold. The identified wafers may be separated for rework to correct the surface defects such as hotspots and improve manufacturing yield without requiring additional equipment. In one embodiment, the surface height metric is a maximum variation from a moving average surface height. In one embodiment, yield data is correlated with surface height information to determine a threshold value corresponding to defective circuit die.
申请公布号 US2006258023(A1) 申请公布日期 2006.11.16
申请号 US20050125863 申请日期 2005.05.10
申请人 LSI LOGIC CORPORATION 发明人 ROLOFSON KIRK;GWYNN BRENT;FENRICK MICHAEL
分类号 H01L21/66;G06K9/00 主分类号 H01L21/66
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