| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor device with a suppressed circuit area and an improved voltage-withstanding characteristic. SOLUTION: The semiconductor device includes a PMOS transistor QP<SB>2</SB>with the source connected to a power line L<SB>VDD</SB>, an NMOS transistor QN<SB>2</SB>with the source connected to the ground line L<SB>GND</SB>and the drain connected to the drain of the PMOS transistor QP<SB>2</SB>, dummy NMOS transistors QN<SB>3</SB>-QN<SB>n</SB>with the source connected to the ground line L<SB>GND</SB>and the drain connected to the drains of the PMOS transistor QP<SB>2</SB>and NMOS transistor QN<SB>2</SB>, and a gate potential control circuit 30 for controlling the gate potentials of the dummy NMOS transistors QN<SB>3</SB>-QN<SB>n</SB>based on the potential of the power line L<SB>VDD</SB>. COPYRIGHT: (C)2007,JPO&INPIT
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