| 摘要 |
PROBLEM TO BE SOLVED: To provide an instruction execution method using a high performance RISC based superscalar processor suitable for being realized with a microprocessor. SOLUTION: A microprocessor, for fetching an instruction set from an instruction store to interpret and execute the instruction set, is provided with an instruction set acquisition means for acquiring a predetermined instruction set to be executed which includes an instruction for referring to a register, a data store means for storing data in a plurality of registers including a predetermined register and a temporary register, and an execution means which is coupled to the instruction set acquisition means, for executing the predetermined instruction sets sequentially, and instructs for data processed by an instruction executed out of order to be stored in the temporary register, wherein a register referred to by an instruction executed out of order is the predetermined register. COPYRIGHT: (C)2007,JPO&INPIT
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