发明名称 DRAM cells with vertical transistors
摘要 The invention includes a semiconductor structure having U-shaped transistors formed by etching a semiconductor substrate. In an embodiment, the source/drain regions of the transistors are provided at the tops of pairs of pillars defined by crossing trenches in the substrate. One pillar is connected to the other pillar in the pair by a ridge that extends above the surrounding trenches. The ridge and lower portions of the pillars define U-shaped channels on opposite sides of the U-shaped structure, facing a gate structure in the trenches on those opposite sides, forming a two sided surround transistor. Optionally, the space between the pillars of a pair is also filled with gate electrode material to define a three-sided surround gate transistor. One of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. The invention also includes methods of forming semiconductor structures.
申请公布号 US2006258109(A1) 申请公布日期 2006.11.16
申请号 US20060490294 申请日期 2006.07.20
申请人 发明人 JUENGLING WERNER
分类号 H01L27/108;H01L21/336 主分类号 H01L27/108
代理机构 代理人
主权项
地址