发明名称 High Speed Data Recording With Input Duty Cycle Distortion
摘要 Data from both a positive edge sample and negative edge sample are used to determine a data bit. The primary and secondary clocks capture two copies of the data. A sample is taken with a positive edge of one clock and the negative edge of the other clock each bit period. These two captured data values are combined along with the data value captured by the previous negative edge to determine the data bit value. The captured data may be dynamically de-skewed previous to being clocked into a buffer based on the clock edges sampling the data.
申请公布号 US2006259820(A1) 申请公布日期 2006.11.16
申请号 US20060382835 申请日期 2006.05.11
申请人 SWOBODA GARY L 发明人 SWOBODA GARY L.
分类号 G06F11/00 主分类号 G06F11/00
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