REDUCED PARALLEL AND PIPELINED HIGH-ORDER MIMO LMMSE RECEIVER ARCHITECTURE

摘要

Disclosed is a LMMSE receiver that restores orthogonality of spreading codes in the downlink channel for a spread spectrum signal received over N receive antennas. The FFT-based chip equalizer tap solver reduces the direct matrix inverse of the prior art to the inverse of some submatrices of size NxN with the dimension of the receive antennas, and most efficiently reduces matrix inverses to no larger than 2x2. Complexity is further reduced over a conventional Fast Fourier Transform approach by Hermitian optimization to the inverse of submatrices and tree pruning. For a receiver with N=4 or N=2 with double oversampling, the resulting 4x4 matrices are partitioned into 2x2 block sub-matrices, inverted, and rebuilt into a 4x4 matrix. Common computations are found and repeated computations are eliminated to improve efficiency. Generic design architecture is derived from the special design blocks to eliminate redundancies in complex operations. Optimally, the architecture is parallel and pipelined.