| 摘要 |
Memory systems, modules, controllers, and methods using dedicated data and/or control buses are provided to offer benefits comparable with usual point-to-point buffered solutions by making the data and command/address buses actually support the same bit rate while using relatively simple UDIMMs(Unbuffered Dual In-line Memory Module). Memory devices(300) are arranged on a memory module as sets. Each set includes at least one memory device. Dedicated serial data and/or control buses(330,350) respectively couple the memory device sets with an external memory controller(360). The dedicated serial data and/or control buses provide access unbuffered to each memory device from the memory controller. The memory device sets are respectively equipped with the memory devices(320) of the memory modules. Each memory device is coupled with the related control bus, and equipped with a packet decoder for decoding address and/or command data from packets received through the control bus.
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