发明名称 |
Isolation trench perimeter implant for threshold voltage control |
摘要 |
A method of forming isolation trenches in a semiconductor fabrication process to reduce transistor channel edge effect currents includes forming a masking structure overlying a substrate to expose a first area of the substrate. Spacers are formed on sidewalls of the masking structure. The spacers cover a perimeter region of the first area thereby leaving a second smaller area exposed. The region underlying the second area is etched to form an isolation trench that is then filled with a dielectric. The spacers are removed to expose the perimeter region. Using the masking structure and the trench dielectric as a mask, an impurity distribution is implanted into a portion of the substrate underlying the perimeter region. The impurity distribution thus surrounds a perimeter of the trench dielectric proximal to an upper surface of the substrate. The perimeter impurity distribution dopant, in a typical case, is p-type for NMOS transistors and n-type for PMOS.
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申请公布号 |
US7135379(B2) |
申请公布日期 |
2006.11.14 |
申请号 |
US20040955658 |
申请日期 |
2004.09.30 |
申请人 |
FREESCALE SEMICONDUCTOR, INC. |
发明人 |
ORLOWSKI MARIUS K.;BURNETT JAMES D. |
分类号 |
H01L21/76 |
主分类号 |
H01L21/76 |
代理机构 |
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