REDUNDANCY SELECTOR CIRCUIT FOR USE IN NON-VOLATILE MEMORY DEVICE

摘要

A redundancy selection circuit of a nonvolatile memory device is provided to perform conversion operation defective data bits into redundant data bits among inputted/outputted data bits regardless of the operation speed of the memory device, by including a comparison block detecting whether an input address during a normal operation coincides with one of defective addresses stored in a latch block. A ROM cell array(1810) stores defective addresses, and has plural ROM cells arranged in columns and rows. A ROM controller(1812) selects rows of the ROM cell array in sequence during power-up. A sense amplifier block(1814) senses and amplifies data bits from each ROM cell of the successively selected rows according to the control of the ROM controller. A latch block(1818) receives data bits sensed by the sense amplifier block through a switch circuit, and latches the inputted data bits as defective addresses. A comparison block(1820) detects whether an address inputted during normal operation coincides with one of the defective addresses stored in the latch block. As the rows are selected in sequence, the defective addresses of the ROM cell array are transmitted to the latch block through the sense amplifier block.