| 摘要 |
Structures and methods for DEAPROM memory with low tunnel barrier intergate insulators are provided. The DEAPROM memory includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposes the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator having a tunnel barrier of less than 1.5 eV. The low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of NiO, Al<SUB>2</SUB>O<SUB>3</SUB>, Ta<SUB>2</SUB>O<SUB>5</SUB>, TiO<SUB>2</SUB>, ZrO<SUB>2</SUB>, Nb<SUB>2</SUB>O<SUB>5</SUB>, Y<SUB>2</SUB>O<SUB>3</SUB>, Gd<SUB>2</SUB>O<SUB>3</SUB>, SrBi<SUB>2</SUB>Ta<SUB>2</SUB>O<SUB>3</SUB>, SrTiO<SUB>3</SUB>, PbTiO<SUB>3</SUB>, and PbZrO<SUB>3</SUB>. The floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator. And, the control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.
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