| 摘要 |
There is disclosed a sample selection and data alignment circuit that is able to recover (retime) a data on a predefined phase of a multiphase clock signal. A plurality of over sampled signals (G<SUB>0</SUB>, . . . , G<SUB>n-1</SUB>) is obtained by over sampling an incoming serial binary data (bits) stream with the n phases (G<SUB>0</SUB>, . . . , G<SUB>n-1</SUB>) of a multiphase clock signal. A reliable over sampled signal is selected according to a selected signal (G<SUB>0</SUB>, . . . , G<SUB>n-1</SUB>) generated by an edge detector which designates which over sampled signal is the best for subsequent processing.
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