发明名称 Memory controller for synchronous burst transfers
摘要 A processing system includes a processor, a memory controller, and a memory subsystem. The memory controller includes a processor interface, a memory data interface, sequential transfer circuitry, and transaction processing logic. Randomly accessed data units of a first size are synchronously exchanged between the memory data interface of the memory controller and the memory subsystem via a transfer sequence comprising a predetermined plurality of sequential transfers of data units of a size smaller than the first size.
申请公布号 US7136971(B2) 申请公布日期 2006.11.14
申请号 US20030361082 申请日期 2003.02.10
申请人 INTEL CORPORATION 发明人 LITAIZE DANIEL;SALINIER JEAN-CLAUDE;MZOUGHI ABDELAZIZ;ELKHLIFI FATIMA-ZAHRA;LALAM MUSTAPHA;SAINRAT PASCAL
分类号 G06F12/00;G06F12/08;G06F15/80;G11C7/10 主分类号 G06F12/00
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