Parallel input/output self-test circuit and method

摘要

A parallel data transmission test system can include a receiver section ( 100 ) having input selector circuits ( 104 - 0 to 104 -N) that provide a received test data to logic adjust circuits ( 106 - 0 to 106 -N) that "logically align" multiple incoming test values to remove intentionally introduced logic difference (e.g., inversion) with respect to one another. Result combining circuit ( 108 ) can logically combine output data values and provide a resulting sequence to a pattern sequence test circuit ( 110 ).