发明名称 Retry cancellation mechanism to enhance system performance
摘要 A method, an apparatus, and a computer program are provided for a retry cancellation mechanism to enhance system performance when a cache is missed or during direct memory access in a multi-processor system. In a multi-processor system with a number of independent nodes, the nodes must be able to request data that resides in memory locations on other nodes. The nodes search their memory caches for the requested data and provide a reply. The dedicated node arbitrates these replies and informs the nodes how to proceed. This invention enhances system performance by enabling the transfer of the requested data if an intervention reply is received by the dedicated node, while ignoring any retry replies. An intervention reply signifies that the modified data is within the node's memory cache and therefore, any retries by other nodes can be ignored.
申请公布号 US2006253662(A1) 申请公布日期 2006.11.09
申请号 US20050121121 申请日期 2005.05.03
申请人 BASS BRIAN M;DIEFFENDERFER JAMES N;TRUONG THUONG Q 发明人 BASS BRIAN M.;DIEFFENDERFER JAMES N.;TRUONG THUONG Q.
分类号 G06F13/00;G06F12/00 主分类号 G06F13/00
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