| 摘要 |
A clock recovering circuit for generating an output clock locked to an analog input signal includes: a phase detection unit for receiving the analog input signal and the feedback clock for generating a phase error signal according to the analog input signal and the feedback clock; a loop filter coupled to the phase detector for filtering the phase error signal and generating a control signal; a numerically controlled oscillator (NCO) coupled to the loop filter for generating a first clock and an index signal according to the control signal; a delay locked loop (DLL) coupled to the NCO for receiving the first clock and generating a plurality of second clocks; and a multiplexer coupled to the NCO and the DLL for selecting one of the second clocks as the output clock according to the index signal.
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