| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a clock data recovery circuit with circuit loop disablement. <P>SOLUTION: The present invention relates to a clock data recovery circuit (48) including a first circuit (100), a second circuit (102) and a third circuit (104). The first circuit (100) is configured to receive data and a clock signal, to detect transitions in the data and to provide a first signal based on the clock signal and the transitions in the data. The second circuit (102) is configured to receive the first signal and to provide a first shift signal based on the first signal. The third circuit (104) is configured to receive the first shift signal, wherein the first circuit (100), the second circuit (102) and the third circuit (104) are configured to form a first circuit loop and the third circuit is configured to disable the first circuit loop and to shift the clock signal based on the first shift signal. <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
