| 摘要 |
An integrated semiconductor memory device and a synchronizing method thereof are provided to synchronize a signal with a clock signal with high reliability, by including a control circuit for generating an internal read command signal on the basis of a read command signal applied from the outside. A first control port applies a configuration signal(MR). A clock generation circuit generates a first clock signal(CLKD), and a second clock signal(DLLCLK) time-shifted from the first clock signal. A first control circuit(31) generates a first control signal(iPoint) and an internal clock signal(CLKIP) delayed from the first clock signal, and generates the first control signal synchronized with the internal clock signal at the time of depending on the configuration signal. A second control circuit(32) generates a second control signal(oPoint) synchronized with the second clock signal. A latch circuit(33) latches a first command signal(PAR) and outputs a second command signal(OUT). When the latch circuit is driven by the first point signal, the first command signal is latched in synchronization with the internal clock signal in the latch circuit. When the latch circuit is driven by the second control signal, the second command signal is outputted from the latch circuit in synchronization with the second clock signal.
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