发明名称 MEMORY CONTROL SYSTEM
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a memory control system which generates no unnecessary period of time for clocking while reducing an influence of the size of an image block in image-data compression processing and is simple in structure and computation. <P>SOLUTION: The memory control system is provided with; (a) a memory part having a plurality of banks; (b) one or more bus masters; (c) an arbiter part which outputs a master selection signal, which selects a bus master which permits access, and drive information inputted from the selected bus master; (d) a bus master selection part which outputs the block mode signal of the bus master selected by the master selection signal, block information and data corresponding to the block; and (e) a memory controller which controls to store and read each of line groups of the block sequentially in/from each of the banks different from each other. A second RAS signal is inputted between the RAS signal and a CAS signal to the first bank. <P>COPYRIGHT: (C)2007,JPO&INPIT</p>
申请公布号 JP2006309702(A) 申请公布日期 2006.11.09
申请号 JP20050336220 申请日期 2005.11.21
申请人 C & S TECHNOLOGY CO LTD 发明人 JEONG KYUNG AH
分类号 G06F12/06;G06F12/00;G06F12/02;G06T1/60;H04N19/423;H04N19/50;H04N19/503 主分类号 G06F12/06
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