| 摘要 |
Techniques for determining a location-based on-chip variation factor for an integrated circuit device are provided. A first on-chip variation factor is computed for at least one of two or more signal paths of the integrated circuit device. The first on-chip variation factor is a function of a timing delay. A second on-chip variation factor is also computed for the integrated circuit device. The second on-chip variation factor is a function of a physical layout of the integrated circuit device. The first on-chip variation factor and the second on-chip variation factor are combined for the at least one of the two or more signal paths to determine a location-based on-chip variation factor for the at least one of the two or more signal paths.
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