发明名称 |
Apparatus and method for entering and exiting low power mode |
摘要 |
An apparatus for entering and exiting low power mode comprising a processor having a cache; a power management mechanism connected to said processor for controlling a plurality of power management states, at least one of said power management states being a low latency low power state; a memory subsystem including a self sustaining mechanism connected to said processor for retaining data during said low power state; a pre-fetching means in said memory subsystem for loading instructions into a cache prior to entering said low power state; a disabling mechanism in said processor for disabling any interrupts that may disturb said pre-fetched instructions; an enabling means in said memory subsystem for initiating the self sustaining operation of said memory subsystem; a detecting means connected to said processor for sensing a trigger to exit from said low power state; and a restoring means in said power management mechanism for restoring the clock of said apparatus; thereby said processor disabling said self sustaining operation and resuming normal operation at the end of said low power state.
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申请公布号 |
US2006253716(A1) |
申请公布日期 |
2006.11.09 |
申请号 |
US20050264301 |
申请日期 |
2005.10.31 |
申请人 |
DHIMAN GAURAV;KAPOOR GAURAV |
发明人 |
DHIMAN GAURAV;KAPOOR GAURAV |
分类号 |
G06F1/00 |
主分类号 |
G06F1/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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