| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a leaked carrier power reduction circuit at low cost with simple circuit configuration. <P>SOLUTION: Correction information for minimizing a sum between a baseband signal demodulated by a main quadrature demodulator 26 and a baseband signal demodulated by a sub quadrature demodulator 27 and whose DC component is blocked is generated, and a baseband signal received by a main quadrature demodulator 17 is corrected in response to the correction information. A deviation between a center voltage of the main quadrature demodulator 17 and the DC component of the baseband signal received by the main quadrature demodulator 17 is automatically minimized while carrying out the quadrature modulation to reduce the leaked carrier power in the main quadrature modulator 17. Further, since a control unit 1, delay circuits 2, 3, 8, 9, bit adders 4, 5, bit inverters 6, 7, D/A converters 10 to 13, and A/D converters 28 to 31 are configured by digital circuits, the number of analog circuits can be decreased to the utmost, and the leaked carrier power reduction circuit is immune to a temperature change and a secular change, needs no correction circuit, and can be realized at low cost with simple circuit configuration. <P>COPYRIGHT: (C)2007,JPO&INPIT |
