发明名称 |
VERIFICATION DEVICE AND VERIFICATION METHOD FOR LOGIC SYSTEM, AND STORAGE MEDIUM AND COMPUTER PROGRAM |
摘要 |
PROBLEM TO BE SOLVED: To reduce man-hours for analyzing a cause of error found in dynamic simulation. SOLUTION: This verification device or the like for a logic system described by a hardware description language has: a test bench production means executing the dynamic simulation; a static verification means executing static verification; and an error part specification means specifying an error part from results of the dynamic simulation and the static verification. COPYRIGHT: (C)2007,JPO&INPIT
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申请公布号 |
JP2006309576(A) |
申请公布日期 |
2006.11.09 |
申请号 |
JP20050132619 |
申请日期 |
2005.04.28 |
申请人 |
CANON INC |
发明人 |
SHIMIZU YASUYO |
分类号 |
G06F17/50;G01R31/28;H01L21/82 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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