发明名称 Transient pulse, substrate-triggered biCMOS rail clamp for ESD abatement
摘要 A circuit for protecting a circuit device against electrostatic discharge (ESD), power line, and voltage supply line surges. A transistor, diode, resistor, and capacitor are configured to clamp voltage pulses between the power and ground lines. The circuit is constructed using a single bipolar npn transistor formed using an isolated p-well.
申请公布号 US2006250732(A1) 申请公布日期 2006.11.09
申请号 US20050123305 申请日期 2005.05.06
申请人 PEACHEY NATHANIEL M 发明人 PEACHEY NATHANIEL M.
分类号 H02H9/00 主分类号 H02H9/00
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