| 摘要 |
A sense amplifier circuit of a memory device is provided to enable high speed operation of the memory device by reducing tRP(RAS precharge time). In a sense amplifier circuit of a memory device, a sense amplifier(200) is shared by adjacent first and second memory cell array blocks. A first equalization unit(400) equalizes the voltage levels of a bit line pair connecting the first memory cell array block and the sense amplifier in response to a first signal. A second equalization unit(400a) equalizes the voltage levels of a bit line pair connecting the second memory cell array block and the sense amplifier in response to a second signal. A third equalization unit(400b) equalizes the voltage levels of a bit line pair connecting a second isolation unit(100a) and the sense amplifier in response to a third signal. A first isolation unit(100) and the second isolation unit isolate the bit line pair connecting the first and second memory cell array blocks and the sense amplifier, respectively. The first equalization unit and the second equalization unit are independently driven by the first signal and the second signal, respectively.
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