| 摘要 |
An input address control circuit is provided to reduce unnecessary current consumption by disabling a row address path, an address buffer and an address latch part in a 4 bank active operation. An address buffer part(100) compares an input address with a reference voltage when a clock enable signal is enabled, and outputs an input signal by buffering a signal according to the comparison result. An address latch part(110) outputs an output signal by latching the input signal when an internal clock signal is enabled. A global address generation part(120) generates a column address by latching the output signal, and generates a row address by delaying a signal assembling a latch signal latching the output signal and a row address control signal while a row active signal is enabled. The global address generation part comprises a row address control part(122) for disabling an output path of the row address by disabling the row address control signal when all banks are enabled by receiving a bank active signal indicating an active state of a bank.
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