Circuit to switch between clock signals and relative process

摘要

A circuit is described for switching between at least a first clock signal (CK1) and a second clock signal (CK2) belonging to a plurality of clock signals (CK1...CKn) available in an electronic device in response to the corresponding switch command (CKS), which comprises a selection module (20) to select at a switch instant (t s ) said second clock signal (CK2) in said plurality of clock signals (CK1...CKn) under the control of a signal selector (S) and provide a selected clock signal (CKM). According to the invention said circuit comprises a logic-based filter module (30) located downstream of said selection module (20) and configured to produce an outgoing clock signal (CKO') filtered under the control of a filter signal (SR) and also includes a control module (40) configured to receive said switch command (CKS) and to send said select signal (S) to said selection module (20) delaying said switch instant (t s ) by a first interval of time (t st ), said control module (40) also being configured to send said active filter signal (SR) for filtering to said filter module (30) in a second interval of time that comprises an edge of the first clock signal (CK1) and an edge of the second clock signal (CK2) that are adjacent to said switching instant (t s ).