| 摘要 |
A semiconductor device having a shallow trench isolation (STI) structure, which is capable of reducing leakage current in a P-FET and improving the device characteristics of a memory device, and a manufacturing method thereof, including a semiconductor substrate having a first area with a first trench formed therein and a second area with a second trench formed therein; a first sidewall oxide layer formed on the inner surface of the first trench; a second sidewall oxide layer, which is thinner than the first sidewall oxide layer, formed on the inner surface of the second trench; a liner formed on the surfaces of the first and second sidewall oxide layers; and a dielectric material that fills the first and second trenches. <IMAGE> |
