发明名称 System and method for emulating a logic circuit design using programmable logic devices
摘要 The present system provides a number of hardware and software modules that emulate logic circuit designs for simulation purposes. The present system receives an initial logic circuit design and provides algorithms to recode, weight partition and interconnect an emulated logic circuit wherein the features of the original circuit design are preserved. The system further provides a monitoring of the internal signals within the emulated circuit.
申请公布号 US2006247909(A1) 申请公布日期 2006.11.02
申请号 US20050207559 申请日期 2005.08.18
申请人 DESAI MADHAV P;PURANDARE MITRA S;SHARMA HIMANSHU;PATKAR SACHIN B 发明人 DESAI MADHAV P.;PURANDARE MITRA S.;SHARMA HIMANSHU;PATKAR SACHIN B.
分类号 G06F17/50;G06F9/45;G06F9/455 主分类号 G06F17/50
代理机构 代理人
主权项
地址