| 发明名称 |
Method for managing the stress configuration in the channel of a MOS transistor, and corresponding integrated circuit. |
| 摘要 |
The MOS transistor, for example the NMOS transistor (NMOS1) is covered with an upper layer, for example a Contact Etch Stop Layer (BCESL, LCESL, TCESL) having a non-uniform thickness and/or a non-uniform field of stresses.
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| 申请公布号 |
EP1717864(A1) |
申请公布日期 |
2006.11.02 |
| 申请号 |
EP20050290922 |
申请日期 |
2005.04.27 |
| 申请人 |
STMICROELECTRONICS ( CROLLES 2) SAS;KONINKLIJKE PHILIPS ELECTRONICS N.V. |
发明人 |
FIORI, VINCENT;ORAIN, STEPHANE;ORTOLLAND, CLAUDE |
| 分类号 |
H01L29/78;H01L21/8238;H01L27/092 |
主分类号 |
H01L29/78 |
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